1. Related Applications
The present invention is related to our U.S. application Ser. No. 07/991,915 filed May 12, 1992 for a Least Recently Used Four Block Cache Logic System.
2. Field of the Invention
The present invention relates to high speed instruction processors (IPs) that employ high speed cache memory with page-table-look-aside-buffers (TLBs). More particularly, the present invention relates to logic circuitry for managing page-table-look-aside-buffers (TLBs) employed in high speed computing system that use virtual memory main storage units (MSUs).
2. Description of the Prior Art
Large high speed mainframe computers are provided with one or more instruction processors (IPs) in a system that is operable to access one or more main storage units (MSUs). Virtual memory main storage units are under the control of the IPs executive operating system software and are capable of replacing portions of the MSU with data and commands stored in slower but larger mass storage devices. In such large main frame computing systems, the instruction processor may desire to reference a block or blocks of words that do not presently reside in its own high speed primary cache memory. If the words being referenced are not found in the cache memory when an attempt to access the information occurs, the instruction processor must wait in an idle state until the desired word or words in the block or blocks of information is transferred from an MSU to the cache memory of the IP. In a virtual memory processor if the word or words referenced by the IP are not resident in the MSU, then the executive operating system and the control unit of the MSU must fetch a page of words from a slower but larger mass storage device and write the page of words into the MSU where they can be transferred as a block of words to the cache memory of the IP in the form of data and/or commands.
A missed attempt by the IP to reference a word not in its cache memory is nevertheless a missed hit that degrades the performance of the IP. The hit rate of the IP to the cache memory is enhanced by replacing the word portions of the cache memory that was least recently used (LRU) when new information is written into the cache from an MSU. In our aforementioned U.S. application Ser. No. 07/881,915 further enhancement is accomplished by logic circuitry that will write new information into an invalidated memory location of the cache memory first but not a degraded memory location.
When the IP references a page of information not found in its own MSU, a much longer delay occurs for the program presently being run while the page is fetched from a mass storage device in the form of a page of information. To fetch a page, the IP issues an absolute address which is translated in translator circuits of the cache memory of the IP to provide a system real address which contains a translated real page address that is stored in a table. If the system real address does not reside in the table-look-aside-buffers (TLB), it must be translated and written into the TLB. The translation process is lengthy, thus degrades the IPs performance when a new page of information is required.
It would be highly desirable to provide a method and logic means for enhancing the hit rate of the IP absolute addresses in the TLB in order to increase the performance of the IP by increasing the chance that the real page address has been previously translated and resides in the TLB.